1. Field of the invention
The present invention relates to an integrated circuit having one or more devices formed in a high voltage tub, and one or more peripheral devices coupled thereto.
2. Description of the Related Art
Flash memory EEPROM devices are widely used in the semiconductor industry. These provide electrically-erasable programmable read-only memory (EEPROM) cells in an array that includes circuitry for erasing the information stored in a large number of cells at the same time, referred to as "flash erase". This flash erase is accomplished by applying a relatively high erase voltage simultaneously to all of the cells located in a given doped semiconductor tub region. In particular, as flash memory devices are scaled down into the deep-submicron regime, tub erase is being increasingly deployed because it features lower erase current and better reliability performance than the conventional source-side erase scheme. However, tub erase requires that a voltage higher than that required in normal operation to be applied to the flash memory device. For example, in one commercial design, during tub erase a high voltage of 10 to 12 volts is applied to the tub, source and drain, and -6 volts is applied to the control gate of the flash memory device. Therefore, the transistors connected to the tub must withstand the high voltage (e.g., 10 to 12 volts) required for the erase operation.
However, in state-of-the-art CMOS integrated circuit fabrication processes, especially those designed for use at 3.3 volts and below, it is a difficult task to build high voltage (HV) devices to support source/drain voltages of more than 6 volts unless the process complexity is significantly increased. That is, flash memory fabrication processes usually require several additional process steps to build HV devices strong enough to support the high voltages needed during the flash erase. For example, the source/drain to substrate reverse-bias breakdown voltage is usually one limiting factor in the operation of a MOS transistor. To increase this voltage above the nominal level obtained for the devices in the memory array usually requires extra implant steps to form source/drain junctions that have a highly graded dopant profile. This requires several extra process steps to form the HV devices, which prevents tub erase from being widely used, especially for embedded applications; that is, where memory cells and logic transistors are formed on the same integrated circuit.